View TB62217AFG_3154220.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

TB62217AFG 2004-11-12 1 toshiba bicd process integrated circuit silicon monolithic TB62217AFG pwm drive stepping motor driver / brush dc motor driver selectable, dc-dc converter and reset function ic the tb62217fg is a dual stepping motor driver driven by pwm chopper micro step, with 3- channe l step-down dc-dc converters and an external-ic reset function. to drive a two-phase bipolar-type stepping motor, a 16-bit latch and a 16-bit shift register are built into the ic. the ic is suitable for driving stepping motors with low-to rque ripple in a highly efficient manner. in addition, a signal axis can be switched to serve as a pwm driver for two dc motors. by equipping the stepping moto r driver with selectable mixed decay mode for switching the attenuation ratio during chopping, and also equipping it with a dc-dc converter, it is possible for the ic to supply external voltage. with a built-in timer that starts running when the ic is supplied with power, the ic can be used in resetting (initializing) external devices. features ? the following motor combinations can be used. stepper dc large dc (l) dc small dc (s) (1) dual motors ? ? (2) single motor single motor ? (3) single motor ? dual motors (4) ? single motor dual motors (5) ? dual motors ? (6) ? ? quadruple motors note hereafter, dc large will be referred to as dc (l) and dc small will be referred to as dc (s). the large current standard is achieved by shorting a small current h-bridge across two ics. in addition, if the thermal setting is designed to be within the prescribed ther mal range, the initial torque current can be used as the normal operating current. weight: 0.45 g (typ.) 4ufqqjoh.pups " ."9
4johmf .pups
%$.pups.pef %$-bshf %$4nbmm 1vmtftqjlf1fbl " ot
"ot
recommended maximum current " nt
" nt
stationary current " "
TB62217AFG 2004-11-12 2 ? it is possible to supply external voltage by incorporating three step-down 1.5 v to 5.0 v variable dc-dc converters. ? a reset function has been added making it possible to deliver an external reset signal. ? the dmos motor driver output of this monolithic bicd ic is capable of achieving a low on resistance of ron = 0.6 ? ( ? t j = 25c, 0.6a: typ.) ? with two sets of internal 16-bit shif t register and latch, the ic can drive stepping motors using a 4-bit micro step. ? equipped protection circuits: dc-dc converter over curr ent/increased voltage protec tion, motor over current protection and total ic ov er temperature protection. in addition, equipped with power on reset circuit for init ializing the ic when the power is turned on and off. ? package: 64-pin pb-free qfp package with a heat sink (thqfp64-p-1010-0.50) ? motor maximum output pressure: 50 v ? on-chip mixed decay mode enables specific ation of four-stage attenuation ratio. ? chopping frequency can be set by exte rnal oscillator. high-speed chopping is possible at 100 khz or higher. note: when using the ic, exercise great care in regard to thermal conditions. this device is easy damaged by high static volt age (esd). for this reason, please handle with care. please insert an sbd (schottky barrier di ode : recommended "tsb cr s04 ) between "odb " pin and "d-gnd" pin , if using c channel.
TB62217AFG 2004-11-12 3 * pin layout (4-channel dc motor mode , example) t-hqfp64-1010-p-0.50 combinations enclosed in the blue dash ed lines are used when in dc (l) mode (a- and b-axis driv ers in a pair, and c- and d-axis driv ers in a pair). dch driver cch driver ach driver bch driver $?4&-&$5 .(/% 0654% 34% 34% 0654% .(/% /$ /$ .(/% 0654$ 34$ 34$ 0654$ .(/% %(/% &/"#-&4% 5&45 &/"#-&4$ 0%" 5i065 '#" -phjd065 73&'$% &/"#-&4# 73&'"# &/"#-&4" 7. /$ 7%*/ -(/% 7%*/ -(/% /$ /$ /$ 035 04$? 04$?. $$ 1)"4&4" '## 1)"4&4$ 0% 1)"4&4% '#$ 1)"4&4# 0%$ 4-&&1 .(/% 0654" 34" 34" 0654" .(/% /$ /$ .(/% 0654# 34# 34# 0654# .(/% %(/%
TB62217AFG 2004-11-12 4 cautions on connection to the ic pins note1 connect all nc pins (pins left unused) to the lowest potential level (usually to gnd). note2 connect any unused vref pins (28pin,29pin) to gnd. note3 unused data, clock, and strobe input pins ar e pulled down internally, so connect them to gnd. please ensure that noise is not introduced into the external circuit note4 connect any unused rs pins to vm. note5 connect the feedback pins (f ba, fbb, and fbc) to gnd if the corresponding dc-dc converter is not used. note6 always connect the test pin to the lowest potential level (usually to gnd). note 8 if the ic is inserted in an incorrect orientat ion, it will be damaged because a high voltage is applied to low-voltage blocks. to avoid such dama ge, always confirm the position of pin 1 and the position and dimensions of each lead when installing the ic. note 9 the ic has no on-chip ov er voltage protection ci rcuit. avoid applying a voltage higher than any rated voltage (such as maximum ratings) to the ic. note 10 solder the heat sink provided on the bottom surface of the ic to a ground-level pattern arranged for heat release so as to ensure stable operation and efficient heat release. note11 once set up, since the ic is not affected by a logical input from a ?don?t care ? pin even if a voltage is applied to the pin, as long as the app lied voltage is not higher than its rating, no problem (such as a malfunction) will occur. note7: test pin the tb62217fg has a test mode function for inspection at the factory. the test mode reduces the ?initial and normal protection mask time? and ?ort output time? to 1/ 1024 of the respective ratings so as to make the inspection easier. to maintain normal operation, therefore, be sure to c onnect pin 32 to a ground so that it will not be used. conditions to use the test mode input level 32 high standard operation low test mode 32 pin: test 100k ?
TB62217AFG 2004-11-12 5 pin descriptions (initial setup mode) sleep = low supports a write mode for the initial setup or extended setup mode data. (1) pin description (setup mode, that is , initial setup or extended setup mode) (2) pin description (dual ax is stepping motor mode) (3) pin description (single axis stepping motor and single axis dc (l) mode) (4) pin description (single axis steppi ng motor and dual axis dc (s) mode) (5) pin description (dual axis dc (s) and single axis dc (l) mode) (6) pin description (dual axis dc (l) mode) (7) pin description (quadr uple axis dc (s) mode) pin name assignment table

4&561 .0%& 45&1 %vbm
45&1 %$ -
45&1 %vbm%$ 4
%$ -
%vbm %$ 4
%vbm%$ -
di%$ 4
3fnbsl 4-&&1 -
4-&&1 )
4-&&1 )
4-&&1 ) 4-&&1 ) 4-&&1 ) 4 -&&1 ) .(/% .(/% .(/% .(/% .(/% .(/% .(/% 065" 065" 065" 065" 065-"# 065-"# 0654" 34"
34" 34" 34" 34" 34" 34" 34"
34" 34" 34" 34" 34" 34" 065"
065" 065" 065" 065-"# 065-"# 0654" .(/% .(/% .(/% .(/% .(/% .(/% .(/% /$ /$ /$ /$ /$ /$ /$ /$ /$ /$ /$ /$ /$ /$ .(/% .(/% .(/% .(/% .(/% .(/% .(/% 065# +
065# + 065# + 065# + 065-"# + 065-"# + 0654# + 34#
34# 34# 34# 34# 34# 34# 34#
34# 34# 34# 34# 34# 34# 065# ?
065# ? 065# ? 065# ? 065-"# ? 065-"# ? 0654# ? .(/% .(/% .(/% .(/% .(/% .(/% .(/% %(/% %(/% %(/% %(/% %(/% %(/% %(/% 17 (odc) odc odc o dc odc odc odc 18 (fbc) fbc fbc fbc fbc fbc fbc 19 (odb) odb odb odb odb odb odb 20 (fbb) fbb fbb f bb fbb fbb fbb 21 cc cc cc cc cc cc cc 22 osc_d osc_d osc_d osc_ d osc_d osc_d osc_d 23 nc nc nc nc nc nc nc 30 nc nc nc nc nc nc nc 25 vdin1 vdin1 vd in1 vdin1 vdin1 vdin1 vdin1 26 vdin2 vdin2 vd in2 vdin2 vdin2 vdin2 vdin2 27 vm vm vm vm vm vm vm 28 (vref ab) vref ab vref ab vref ab vref lab vref lab vref sab 29 (vref cd) vref cd vref lcd vref scd vref scd vref lcd vref scd 30 (fba) fba fba f ba fba fba fba 31 (oda) oda oda oda oda oda oda
TB62217AFG 2004-11-12 6

4&561 .0%& 45&1 %vbm
45&1 %$ -
45&1 %vbm%$ 4
%$ -
%vbm %$ 4
%vbm%$ -
di%$ 4
3fnbsl 32 test test test test test test test connect to gnd 33 dgnd1 dgnd1 dgnd1 dgnd1 dgnd1 dgnd1 dgnd1 34 mgnd mgnd mgnd mg nd mgnd mgnd mgnd 35 (out c ? ) out c ? out lcd ? out sc ? out sc ? out lcd ? out sc ? 36 (rs c1) rs c1 rs c1 rs c1 rs c1 rs c1 rs c1 37 (rs c2) rs c2 rs c2 rs c2 rs c2 rs c2 rs c2 38 (out c + ) out c + dout lc( out sc( out sc( out lcd( out sc( 39 mgnd mgnd mgnd mg nd mgnd mgnd mgnd 40 nc nc nc nc nc nc nc 41 nc nc nc nc nc nc nc 42 mgnd mgnd mgnd mg nd mgnd mgnd mgnd 43 (out d() out d( out lcd( out sd( out sd+ out lcd+ out sd+ 44 (rsd1) rsd1 rsd1 rsd1 rsd1 rsd1 rsd1 45 (rsd2) rsd2 rsd2 rsd2 rsd2 rsd2 rsd2 46 out d- out d- out lcd- out sd- out sd- out lcd- out sd- 47 mgnd mgnd mgnd mg nd mgnd mgnd mgnd 48 c_select c_select c_select c_select c_select c_select c_select 49 - - - enable sd enable sd - enable sd 50 - strobe cd enable lcd enable sc enable sc enable lcd enable sc 51 th_out th_out th_out th_out th_out th_out th_out 52 logic out logic out logic out logic out logic out logic out logic out 53 - - - - - - enable sb 54 strobe ab strobe ab strobe ab strobe ab enable lab enable lab enable sa 55 nc nc nc nc nc nc nc 56 lgnd lgnd lgnd lgnd lg nd lgnd lgnd agnd (lgnd) 57 lgnd lgnd lgnd lgnd lg nd lgnd lgnd agnd (lgnd) 58 nc nc nc nc nc nc nc 59 ort ort ort ort ort ort ort 60 osc_m osc_m osc_m osc_m osc_m osc_m osc_m 61 - data cd - phase sd phase sd - phase sa $-,$% 1)"4&-$% 1)"4&4$ 1)"4&4$ 1)"4&-$% 1)"4&4$ %"5""# %"5""# %"5""# %"5""# 1)"4&4% $-,"# $-,"# $-,"# $-,"# 1)"4&-"# 1)"4& -"# 1)"4&4# -: don?t care
TB62217AFG 2004-11-12 7 note: h-bridge combination (connection method) for each type of motor driver note1: when driving a dc motor in dc (l) mode, avoid an impedance difference outside the ic. note2: if the impedance of wiring to mu tually connected output transistors is unbalanced, the current that flows through the transistor also becomes unbalanced and ma y exceed the maximum rating of the transistor, thus damaging the transistor. stepping motor single motor pgnd r s pin r rs v m load pgnd a-phase ? the white circle indicates an ic pin. pgnd r s pin load pgnd r s pin v m dc (l) single motor mutually connected outside the ic r s pin r rs v m load b-phase r rs
TB62217AFG 2004-11-12 8 note load pgnd r s pin r rs v m dc (s) single motor ? the white circle indicates an ic pin.
TB62217AFG 2004-11-12 9 1. overall block diagram protection circuits isd unit tsd circuit por circuit (vm) out x current setting circuit current feedback circuit chopping reference circuit 16-bit shift register 4-bit sine d/a (angle control) torque control r s comp circuit output control unit waveform shaping circuit chopping waveform generating circuit current control 16-bit latch vrs unit osc_m stepping motor dc motor dc motor select odb fbb dc/dc converter dc/dc cnv a oda fba cc cselect oscd vsd unit por unit (cc) logic out thermal detect th_out dc/dc converter dc/dc cnv b odc fbc current control data logic circuit extended setup unit init setup unit 16-bit latch data selector * * these items are provided only on the a- and b-axis inputs. dc/dc selector high-voltage wiring (v m ) logic data analog data ic pin clk strobe v ref r s v m sleep ort data dc/dc converter dc/dc cnv c vm-vdd regulator reset unit outputs unit (h-bridge)
TB62217AFG 2004-11-12 10 2-1. input equivalent circuits (1) logic input pin (2) vref input pin (3) dc/dc feed back pin (fbx) cc lgnd in 150 ? to the internal logic gnd 100 k ? 21 * 57 * 64: phase sb 63: phase sd 62: phase sc 61: phase sa 54: enable sa 53: enable sb 50: enable sc 49: enable sd 1: sleep : fba : fbb : fbc 150 ? 30 20 57 18 1.5 v 2.01 v 1.05 v cc : vref ab : vref cd to the da circuit gnd 2 21 28 29 56 57 56
TB62217AFG 2004-11-12 11 2-2. stepping motor logic unit (with the same functions for both an a-/b-axis pair and a c-/d-axis pair) function this circuit receives step current setting data entered from the data pin and transf ers it to the subsequent stage. it is enabled when the sleep pin is high. (if th e sleep pin is low, the ic enters the initial setup or extended setup mode.) once ort is released, driving the sleep pin high puts the ic in a write mode for stepping motor current control data. driving the sleep pin from high to low and back to high clears any latched motor control data (to all low). step current setting data logic circuit and setup logic b unit side mixed decay timing 16-bit shift register current feedback circuit (trq setting) da circuit output control circuit data clk strobe out p ut control circuit da circuit torque 2 bits decay 2 bits b unit side current 4 bits b unit side phase 1 bit b unit side decay 2 bits a unit side current 4 bits a unit side phase 1 bit a unit side current control 16-bit latch a unit side mixed decay timing b-phase information a-phase information sleep = h 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
TB62217AFG 2004-11-12 12 2-3. initial setup logic unit (available only for the a- / b-axis pair) function this circuit is used to set up driver functions (initial setup) according to signals entered from the data pin. the functions that can be set up include motor re-c onfiguration, digital tbla nk, dc-dc converter on/off setting, and dc motor mode vref (gain) setting. note: do not use the test mode. keep all the corres ponding bits and any unused pins at a low level. note: the setting entered in initial setup mode is in effect if the data signal is low when the strobe signal is supplied. the initial setup mode data is cleared at por (power-on reset). logic circuit and setup logic 16-bit shift register data ab clk ab strobe ab sleep = l initial setup 16-bit latch motor select (3 bit) tblank cd (2 bit) dcdc select (3 bit) dc vref gain (2 bit) test (3 bit) tblank ab (2 bit) no use (1 bit) l 16 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
TB62217AFG 2004-11-12 13 2-4. extended setup logic unit (available only for the a- and b-axis pair) function this circuit sets up the monitor functions of the driver ic internal circuits according to a signal entered from the data pin. note: the internal-signal monitoring setting (entered in extend ed setup mode) is in effect if the data signal is high when the strobe signal is supplied. data for the exten ded setup mode is cleared at por (power-on reset). extended setup logic 16-bit shift register data ab clk ab strobe ab shut down select (4 bit) reset mask (3 bit) pre tsd (2 bit) no use (1 bit) sleep = l extended setup 16-bit latch shut down mask (4 bit) isd time (1 bit) reserved h 16 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
TB62217AFG 2004-11-12 14 3. current feedback circuit and current setting circuit for motor driver function the current setting circuit is used to set the referenc e voltage of the output current using the step current setting data entered from the serial input pin. the current feedback circuit is used to deliver a signal to the output control circuit when the output current reaches the set current. this is done by comparing th e reference voltage delivered from the current setting circuit with the potential difference generated when current flows through the current sense resistor (rrs) connected between rs and vm. the chopping waveform generator, to which a capacitor is connected, generates the osc m (osc-clk) as a chopping frequency reference. if the osc_m pin becomes open, the open condition detectio n function works, thus shutting down the ic. if the pin is shorted to gnd when the ic starts operating, the detection function also works and the ic does not operate. note: the re comp circuit compares the set current wi th the output current and generates a signal when the output current reaches the set current. waveform shaper circuit v ref chopping reference waveform generator circuit oscm output control unit mixed decay timing circuit output stop signal (all off) chopping reference generator circuit torque control circuit current setting circuit torque 0.1 current 0~3 from the logic unit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 step current selector circuit 4-bit da circuit r s comp circuit v m r s nf (set current reached signal) current feedback circuit v rs circuit 1 (detects voltage difference between r s and v m ) 100% 85% 70% 50% dsc open short detect unit osc_d c oscm r rs
TB62217AFG 2004-11-12 15 4. output control circuit, current feedba ck circuit, and current setting circuit for motor driver isd circuit output circuit por circuit (vm) v m tsd circuit logic v sd : dc-dc output voltage monitor v mr : v m power monitor i sd : over current protection circuit t sd : over-temperature protection circuit protection circuits latched-data clear signal output control circuit phase decay mode mixed decay timing circuit output reset signal output driver circuit nt set current reached signal reset signal selector circuit charge start mixed decay timing u1 u2 l1 l2 current feedback circuit current setting circuit osc counter osc counter (2) chopping reference generator circuit step current setting data logic circuit output stop signal output control signal cc monitoring circuit vsd circuit vm-v cc regulator cc th_out
TB62217AFG 2004-11-12 16 5. output equivalent circuit for motor driver the motor output h switch block consists of the upper p-channel demos fet and lower n-channel demos fet. each output demos fet is connected to an over current sense circuit (isd detection circuit) in parallel. v m u1 l1 u2 l2 to v m from output control circuit out a out a r sa r rs a m mgnd out b out b r rs b r sb output driver circuit u1 u2 l1 l2 phase a from output control circuit u1 l1 u2 l2 output driver circuit u1 u2 l1 l2 phase b
TB62217AFG 2004-11-12 17 6. dc-dc converter circuit when an open detection circuit is available, osc_d pin is set to open, the ic shuts down. if the pin is shorted to gnd at startup, the ic fails to star t operating. (it does not detect in a default.) in the dc-dc converter operating mode, channel b starts operating before channel a or c. di maximum rating "di n" #di n" $di n" vsd dc-dc converter a control circuit vdin osc_d rdca1 rdca2 c_dc_a (100 f) to output c osc_d (120 pf) lda (330 h) fba cr control circuit oda dc-dc converter b control circuit rdcb1 rdcb2 c_dc_b (100 f) to output ldb (330 h) fbb odb dgnd dgnd a ch vsd dc-dc converter c control circuit rdcc1 rdcc2 to output ldc (330 h) fbc odc vsd b ch c ch c_dc_c (100 f) t sbd t please insert a sbd( schottky barrier diode : recommended "tsb crs04) between "odb" pin to "d-gnd" pin.
TB62217AFG 2004-11-12 18 7. reset circuit (ort) this circuit has an open-drain output. if the output is pulled up with a resistor to the supply voltage, its level becomes low (internally on) at reset and high (internally hi-z) during normal operation (at a non-reset). 8. dc-dc converter select circuit (c_select) * : each internal circuit resistance varies by 30%. 9. set temperature detection output pin (th-out) it is not necessary to connect a pull-up resist or when choosing analog output mode ( terminal :open) 10. internal logic signa l select output pin (logic out) both the th-out and logic out circuits have th e same open-drain circuit as the ort circuit. if their output pins are pulled up with a resistor to the supply voltage, their levels become low (internally on) at reset and high (internally hi-z) during normal operation (at non-reset). ort 1 k ? dc/dc conv 3.3 v c_select cc 200 k ? to internal 5 v supply voltage 150 ? ? is added if the voltage is 2.5 v +dd 5)pvu
TB62217AFG 2004-11-12 19 16-bit serial input signals three different pieces of data can be entered and se t up by combining the clk, data, strobe and sleep pin inputs. (1) extended setup mode (for setting up protection circuits) (2) initial setup mode (for setting up motor drive modes) (3) stepping motor drive mode (normal drive mode) setup mode specifications (initial setup and extended setup modes) note: the internal-signal monitoring setting (entered in extend ed setup mode) is in effect if the data signal is high when the strobe signal is supplied. if the data signal is lo w, initial setup is in effect (initial setup mode). 0 sleep data clk strobe 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
TB62217AFG 2004-11-12 20 (1) extended setup mode function (write enabled only when sleep = l and setup select = h) ? in the extended setup mode, the pr otection circuits are set up and a monitor setup (output of a lo_out pin) of a shutdown signal etc. is performed. data bit name function setting default value 0 sd select 0 0 1 sd select 1 0 2 sd select 2 0 3 sd select 3 selecting a signal at shut-down these 4 bits select what shut-down signal to produce. see the next item for explanations about the 4-bit data combinations. 0 4 unused ? ? 0 5 dcdc vsd sd mask 0 6 motor isd sd mask 0 7 tsd sd mask shut-down signal mask 0: normal operation. see the corresponding item below for explanations about the 3-bit data combinations. 0 8 reset mask c 0 9 reset mask b 0 10 reset mask a disabling the reset signal at the shut-down of the corresponding dc-dc converter. 0: normal operation. 1: if the dc-dc converter concerned is shut down: (1) the reset signal is not generated. (2) all dc-dc converters other than the dc-dc converter of interest operate normally. (3) the dc-dc converter concerned returns to normal when the sleep signal changes from low to high. 0 11 pre tsd 0 0 12 pre tsd 1 generating a low signal at the th_out pin at a temperature of the tsd temperature ? x. 12 11 ( bit) 0 0: tsd-20c 0 1: tsd-30c 1 0: tsd-40c 1 1: analog 0 13 unused unused ? 0 14 oscm/d watch dog setting specifying whether to cause osc_m and osc_d to run. 0: off (watchdog disabled) 1: on (watchdog enabled) 0 15 unused unused ? 0
TB62217AFG 2004-11-12 21 [shut-down signal output (sd select)] these 4 bits are used to select what shut-down signal to generate. altern atively, they are used to indicate vendor or version code. the shut-down select signals are released when the sleep signal changes form low to high. data function data (3) data (2) data (1) data (0) bit l l l l generate the shut-down signal when the channel a dc-dc converter is shut down with dc-dc vsd_h or dc-dc vsd_l. l l l h generate the shut-down signal when the channel b dc-dc converter is shut down with dc-dc vsd_h or dc-dc vsd_l. l l h l generate the shut down signal when the channel c dc-dc converter is shut down with dc-dc vsd_h or dc-dc vsd_l. l l h h unused l h l l generate the shut-down signal w hen the dc-dc converter is shut down with ?dc-dc vsd_h?. l h l h generate the shut-down signal w hen the dc-dc converter is shut down with ?dc-dc vsd_l?. l h h l generate the shut-down signal w hen the dc-dc converter is shut down with ?motor isd?. l h l h generate the shut-down signal w hen the dc-dc converter is shut down with ?tsd?. h l l l revision (0) deliver bit 0 of the version code. h l l h revision (1) deliver bit 1 of the version code. h l h l revision (2) deliver bit 2 of the version code. h l h h vender code: always deliver ?detected? in the tb62217fg. h h l l unused h h l h unused h h h l unused h h h h unused * : data (3 to 0) = ?0000? to ?0111? are used to indicate a signal filtered in the internal dead-zone time circuit. [shut-down mask] these 3 bits are used to disable th e shut-down function concerned. (one bit corresponds to one function. when a bit is high, the correspon ding function is disabled. th eir default value is ?llll?.) data (7): if this bit is high, ?tsd? is disabled. data (6): if this bit is hi gh, ?motor isd? is disabled. data (5): if this bit is hi gh, ?dc-dc vsd? is disabled. * : data (4): unused.
TB62217AFG 2004-11-12 22 [reset output mask] these 3 bits are used as a signal to specify whet her to produce the reset when the respective dc-dc converters are shut down. no low signal is produced as the reset even if data (x) = h and one dc-dc channel = h. the default value of these bits is ?l, l, l?. (when a dc-dc converter is shut down, the reset is dr iven low, and all dc-dc channels are turned off.) if the dc-dc converter concerned is shut down: (1) no reset (ort) is produced. (2) all dc-dc converters other than that concerned operate normally (rather than being shut down) (3) changing the sleep signal from low to high restarts the dc-dc converter. data (10): dc-dc converter channel a data (9): dc-dc converter channel b data (8): dc-dc converter channel c [pre tsd] a low signal is generated at the th_out pin if the current temperature is x degrees lower than the tsd temperature. in analog output mode, a very low volt age proportional to the te mperature is generated. (the analog output mode is dedicated for test use; its specification is not guar anteed and therefore it may not be able to be used in usual operation.) data (12, 11) = 0, 0: th_out is generated (low level) at the tsd temperature ? 20 c. data (12, 11) = 0, 1: th_out is generated (low level) at the tsd temperature ? 30 c. data (12, 11) = 1, 0: th_out is generated (low level) at the tsd temperature ? 30 c. data (12, 11) = 1, 1: analog output mode. [revision and vender] the revision and vendor codes are specific to an individual version of product. for example: revision (0, 1, 2) = (l, l, l) and vendor = (h) for toshiba #1.0 revision (0, 1, 2) = (h, l, l) and vendor = (h) for toshiba #1.1 revision (0, 1, 2) = (l, h, l) and vendor = (h) for toshiba #1.2 revision (0, 1, 2) = (h, h, l) and vendor = (h) for toshiba #1.3 revision (0, 1, 2) = (l, l, h) and vendor = (h) for toshiba #2.0 5)pvudibsbdufsjt ujd gpssfgfsfodf
ufnqfsbuvsf 0 $ 7pmubhf<+ "cpvun7 0 $
TB62217AFG 2004-11-12 23 [osc_m/osc_d open-state detection circuit] the osc_m/osc_d open-state detection circuit tries to detect when a capacitor comes off the osc_m or osc_d for some reason by monitoring to see if the freq uency gets out of the rated frequency range. when it detects such an event, it shuts down the ic. the open-state detection circuit is init ially off when the power is turned on. (to cause it to run, a serial signal must be supplied to make the corresponding bit high.) the frequency range setti ngs are stated below. (1) shut down if the current frequency does not fall in the range: osc_m frequency/64 > osc_d frequency > osc_m frequency/2 (2) shut down if the current frequency does not fall in the range: osc_d frequency 32 > osc_m frequency > osc_d frequency 2 example 1: if the osc_m frequency is 800 khz the ic is shut down when osc_d frequency > 400 khz or osc_d frequency < 12.5 khz. 2: if the osc_d frequency is 100 khz the ic is shut down when osc_m frequency > 3200 khz or osc_m frequency < 200 khz.
TB62217AFG 2004-11-12 24 (2) initial setup mode select (write enabled only when sleep = l and setup select = l) data bit name function setting default value 0 motor select0 0 1 motor select1 0 2 motor select2 motor pairing setting (see the corresponding pin assignment table.) d2 d1 d0 0 0 0: stepper 2 0 0 1: stepper 1 + dcl 1 0 1 0: stepper 1 + dcs 2 0 1 1: dcl 1 + dcs 2 1 0 0: dcl 2 1 0 1: dcs 4 0 3 tblank ab 0 4 tblank ab 1 channels a and b noise rejection dead band time setting (see note below.) d4 d3 0 0: (1 fchop) 8 5 0 1: (1 fchop) 8 2 1 0: (1 fchop) 8 3 1 1: (1 fchop) 8 4 0 0 5 tblank cd 0 6 tblank cd 1 channels c and d noise rejection dead band time setting (see note below.) d6 d5 0 0: (1 fchop) 8 5 0 1: (1 fchop) 8 2 1 0: (1 fchop) 8 3 1 1: (1 fchop) 8 4 0 0 7 dc/dc a sw dc-dc converter channel a operation 0: on 1: off (note) 8 dc/dc b sw dc-dc converter channel b operation 0: on 1: off (note) 9 dc/dc c sw dc-dc converter channel c operation 0: on 1: off (note) 10 (a- and b-axis) dc motor vref (gain) channels a and b internal vref attenuation ratio setting for constant current in dc motor mode 0: 1/10 1: 1/20 0 11 (c- and d-axis) dc motor vref (gain) channels c and d internal vref attenuation ratio setting for constant current in dc motor mode 0: 1/10 1: 1/20 0 12 test ic internal test mode setting always keep this bit low. 0 13 test ic internal test mode setting always keep this bit low. 0 14 test ic internal test mode setting always keep this bit low. 0 15 unused ? this bit is not in use. always keep it low. 0 note: the initial setting for data bits 7, 8, and 9 is dete rmined according to the value of c_select when the vm power is turned on.
TB62217AFG 2004-11-12 25 tblank (noise rejection dead band time) the tb62217fg incorporates two different dead band times (b lanking times) for different motors to be driven so as to prevent malfunction be cause of switching noise. (1) analog tblank (for stepping motor mode) the noise rejection dead band time (analog tblank), defined by the motor's ac characteristics, is fixed within the ic. it is used mainly to avoid misjudging irr (diode recovery time) when a stepping motor is driven with constant current. it is fixed within the ic; it cannot be altered. (2) digital tblank (for dc motor mode) unlike the analog tblank, this tblank time, specif ied when the initial setup mode is selected, is generated digitally from an external chopping period. it is used mainly to avoid misjudging the varistor recovery current that occurs when a dc motor is driven by pwm in the dc motor drive mode. if the motor select signal selects the stepping motor mode, the digital tblank is nullified (0 s), thus enabling only the anal og tblank time provided within the ic. because the digital tblank is generated in reference to the osc_m, it can be changed by altering the osc_m. (note that altering the osc_m also changes othe r items (motor chopping frequency, dead band time at the time of starting).) digital tblank time in the initial setup mode, the tblank time can be set to 4 different levels for a-b and c-d pairs as follows: (1) immediately after the phase has changed if the phase changes, the following time is need ed for synchronization with an osc_m edge and internal synchronization. tblank time = time need for synchronization between osc_m and phase + set tblank time = internal processing time (osc_m 1) + synchronization time (below osc_m 1) + set time (2) charging in constant-current operation (limiter operation) tblank time = set tblank time the set tblank time is as follows: tblank ab (0, 1) & tblank cd (0, 1) = : 0 0: osc_m period 5 0 1: osc_m period 2 1 0: osc_m period 3 1 1: osc_m period 4 caution: for #2.0 and after, tblank (0, 0) = osc_m period 5.
TB62217AFG 2004-11-12 26 phase iout digital tblank digital tblank digital tblank phase switching point charge start timing in constant-current control phase switching point digital tblank digital tblank digital tblank timing in dc motor drive mode the digital tblank time begins immediately after the exte rnal phase signal is switched or at the charge start timing of the constant-current chopper. the digital tblank is effective only in the dc motor drive mode. the decay mode for dc motor driving is ?fast decay?. iout = 0 charge
TB62217AFG 2004-11-12 27 (3) data for normal stepping motor operation the tb62217fg signals for normal stepping motor oper ation can be entered in much the same manner as the drive data of th e toshiba tb62202af. data bit name function setting 0 torque a0/b0 1 torque a1/b1 current range setting a1/b1 a0/b0 0 0 : 50% 0 1 : 70% 1 0 : 85% 1 1 : 100% 2 decay mode b0 3 decay mode b1 channel b current attenuation ratio setting (mixed decay mode) b1 b0 0 0 : 12.5% decay mode 0 1 : 37.5% decay mode 1 0 : 75% decay mode 1 1 : fast decay mode(100%) 4 current b0 5 current b1 6 current b2 7 current b3 channel b current setting 4-bit current data (using 4 data bits can divide each step into 16.) (?0000?: all-output off mode) see setting table (3). 8 phase b channel b current phase information 1: out b + is high. 0: out b ? is high. 9 decay mode a0 10 decay mode a1 channel a current attenuation ratio setting (mixed decay mode) a1 a0 0 0 : 12.5% decay mode 0 1 : 37.5% decay mode 1 0 : 75% decay mode 1 1 : fast decay mode(100%) 11 current a0 12 current a1 13 current a2 14 current a3 channel a current setting 4-bit current data (using 4 data bits can divide each step into 16.) (?0000?: all-output off mode) see setting table (4). 15 phase a channel a phase information 1: out a + is high. 0: out a ? is high. 0 sleep 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 strobe clk data the initial setup latch, extended setup latch, or normal motor la tch is selected as a write latch according to the logical leve l of the sleep signal and the polarity of the data signal at an strobe signal edge. if the sleep signal is low, the setup latch is selected when the strobe changes from low to high (initial setup if data = low and extended setup if data = high). if the sleep is high, the normal motor latch is selected. don't care the level of the sleep during data transfer. the stepping motor latches (for both a-b and c-d pairs) are init ialized when the sleep signal changes from high to low or from low to high. all registers are in itialized at por. the pins used to write during sleep include the data ab, clock ab, and strobe ab pins.
TB62217AFG 2004-11-12 28 setting table (1) d0 and d1 torque setting the peak torque current can be switched using 2-bit da ta. (switching is the same for both the a-b and c-d pairs.) data bit name function torque 1 torque 0 setting torque (typ.) 0 0 50% 0 1 70% 1 0 85% 0 1 torque0 torque1 sets current range 1 1 100% setting table (2) d2, d3, d9, and d10 decay mode x1 and x0 settings a value of 37.5% is recommended for a typical condit ion. data of (0, 0) specifies a 12.5% decay mode. data bit name function decay mode 1 decay mode 0 setting decay mode 0 0 mixed decay mode: 12.5% 0 1 mixed decay mode: 37.5% 1 0 mixed decay mode: 75% 2 3 9 10 decay mode a1/a0 decay mode b1/b0 sets mixed decay 1 1 fast decay mode (100%) setting table (3) d4, d5, d6, and d7 current b setting data bit step current b3 current b2 current b1 current b0 set angle (degrees) current (%) 16 1 1 1 1 90 100 15 1 1 1 1 84 100 14 1 1 1 0 79 98 13 1 1 0 1 73 96 12 1 1 0 0 68 92 11 1 0 1 1 61 88 10 1 0 1 0 56 83 9 1 0 0 1 51 77 8 1 0 0 0 45 71 7 0 1 1 1 39 63 6 0 1 1 0 34 56 5 0 1 0 1 28 47 4 0 1 0 0 23 38 3 0 0 1 1 17 29 2 0 0 1 0 11 20 1 0 0 0 1 6 10 4 5 6 7 0 0 0 0 0 0 0
TB62217AFG 2004-11-12 29 setting table (4) d11, d12, d13, and d14 current a setting data bit step current a3 current a2 current a1 current a0 set angle value (degrees) current (%) 16 1 1 1 1 90 100 15 1 1 1 1 84 100 14 1 1 1 0 79 98 13 1 1 0 1 73 96 12 1 1 0 0 68 92 11 1 0 1 1 61 88 10 1 0 1 0 56 83 9 1 0 0 1 51 77 8 1 0 0 0 45 71 7 0 1 1 1 39 63 6 0 1 1 0 34 56 5 0 1 0 1 28 47 4 0 1 0 0 23 38 3 0 0 1 1 17 29 2 0 0 1 0 11 20 1 0 0 0 1 6 10 11 12 13 14 0 0 0 0 0 0 0 setting table (5) d8 and d15 phase a setting (this table applies also to phase b.) the polarity of the phase a current of a ste pping motor is determined as listed below. data bit name functi on phase setting phase 0 out a: l, out a-: h out b: l, out b-: h 8 15 phase b phase a switches phase 1 out a: h, out a-: l out b: h, out b-: l
TB62217AFG 2004-11-12 30 functions of external input pins (1) phase input pin (phase x) this pin indicates the polarity of the h switch us ed in driving a dc motor. pwm can be applied by performing time control (duty control) on this pin. pin no. name function logi cal level setting phase l out x: l, out x-: h 61 64 62 63 phase sa sb sc sd switches phase h out x: h, out x-: l (2) enable input pin (enable x) this pin indicates whether to supply the power to a dc motor to be driven. pin no. name function logical level setting enable l off (all transistors for the h switch are off.) 54 53 50 49 enable sa sb sc sd whether to activate the output h active (3) sleep input pin when the level of this pin is switched from high to low or low to high, all motor drive registers are cleared (all bits of the 16-bit latch for select ing a motor drive are cleared to low). after the ic is shut down in motor isd operation, chan ging the sleep signal from high to low and to high again causes the ic to return to normal. pin no. name function logical level setting sleep l power consumption reduction mode and initial setup mode 1 sleep power saving mode h motor operation mode (4) c_select input pin this pin determines which dc-dc converter to run (o n-off combinations) when the power is turned on. pin no. name function logical level setting phase low a ch: off b ch: off c ch: off mid a ch: on b ch: on c ch: off 48 c_select dc-dc converter mode at start high a ch: off b ch: on c ch: on note: if the c_select pin is on the mid level, channel b is turned on before channel a. if it is high, channel b is turned on before channel c.
TB62217AFG 2004-11-12 31 protection operations (1) when the reset output mask is ?1? in the extended setup mode stop state in the protecti on operations listed above ? shut-down = all the functions stop as a failure related to the entire system occurs. they can be restarted only by initializing using the por when the vm power is turned on again. ? off = only the motor block stops operat ing. it can be restarted by changing the sleep signal from high to low and to high again. ? l pulse: the ort keeps producing low pulses for 40 ms (if oscm = 800 khz). ? dc-dc off = only the dc-dc converter concerned stops oper ating. it can be restarted as stated below depending on the logic level on which the sleep signal is when the conv erter stops operating. (1) if the sleep is low when the dc-dc converter stops, it can be restarted by changing the sleep signal from low to high. (2) if the sleep is high when the dc-dc converter stops, it can be restarted by changing the sleep signal from high to low and to high again. detected error and detection block operation state dc/dc a dc/dc b dc/dc c motor entire ic vsd vsd vsd isd tsd dc/dc a dc/dc b dc/dc c motor reset output reset method not detected not detected not detected not detected not detected normal operation normal operation normal operation normal operation h ? detected not detected not detected not detected not detected dcdc off normal operation normal operation normal operation h sleep/por not detected detected not detected not detected not detected normal operation dcdc off normal operation normal operation h sleep/por not detected not detected detected not detected not detected normal operation normal operation dcdc off normal operation h sleep/por not detected not detected not detected detected not detected normal operation normal operation normal operation off l pulse sleep/por not detected not detected not detected not detected detected shut down shut down shut down shut down l por
TB62217AFG 2004-11-12 32 (2) when the reset output mask is ?0? in the extended setup mode detected error and detection block operation state dc/dc a dc/dc b dc/dc c motor entire ic vsd vsd vsd isd tsd dc/dc a dc/dc b dc/dc c motor reset output reset method not detected not detected not detected not detected not detected normal operation normal operation normal operation normal operation h ? detected not detected not detected not detected not detected shut down shut down shut down shut down l por not detected detected not detected not detected not detected shut down shut down shut down shut down l por not detected not detected detected not detected not detected shut down shut down shut down shut down l por not detected not detected not detected detected not detected normal operation normal operation normal operation off l pulse sleep/por not detected not detected not detected not detected detected shut down shut down shut down shut down l por stop state in the protecti on operations listed above ? shut-down = all the functions stop as a failure related to the entire system occurs. they can be restarted only by initializing using the por when the vm power is turned on again. ? off = only the motor block stops oper ating. it can be restarted by changing the sleep signal from high to low and to high again. ? low pulse: low pulses are generated for 40 ms (if oscm = 800 khz). protection circuit dead band time (example in which the reference clock (osc_m) frequency is 800 khz) protection function block detected protection mask width example: time for oscm = 800 khz reset method tsd entire ic 12 to 16clk 15 to 20 s supplying vm power again dc-dc converter no function is available ? ? isd motor 4 to 8clk 5 to 10 s driving the sleep pin low or supplying vm power again vsd dc-dc converter 12 to 16clk 15 to 20 s supplying vm power again note: to put protection into effect, the protection circui t must keep operating for at least the time stated above.
TB62217AFG 2004-11-12 33 (1) extreme voltage drop protection function vsd (when detected, the ic is shut down) (2) extreme voltage drop protection function vsd during current limiter operation (when detected, the ic is shut down) (3) ic overheat protection function (tsd) (when detected, the ic is shut down) note: a low-pulse period of 40 ms is applied when osc_dm frequency = 800 khz and clock = 1.25 s. 4) motor over current protection function (when detected, only the motor is stopped) set voltage dc-dc converter channel a/b/c output gnd reset output 12~16 clk set voltage + 40% (typ.) set voltage ? 30% (typ.) gnd overheat protection value ic junction temperature gnd reset output 12~16 clk over current motor output current gnd gnd reset output 4~8 clk 32768 clock (40 ms typ.) set voltage dc-dc converter channel a/b/c output reset output osc_d: 3 clk set voltage + 40% (typ.) set voltage ? 15% (typ.) ? 30% gnd limiter state current limiter operation gnd gnd
TB62217AFG 2004-11-12 34 power supply sequence if the c_select pin is driven mid or high the 1st dc-dc converter represents channel b, and the 2nd dc-dc conver ter, channel a or c. note: if the c_select pin specifies that all dc-dc c onverters be off, the ort reset time is 320 ms. if serial data specifies dc-dc converters be turned on after the power is turned on (c_select: low) dc-dc converter channel a operation start channel a protection mask dc-dc converter channel b operation start channel b protection mask dc-dc converter channel c operation start channel c protection mask 100 ms 100 ms 100 ms max 320 ms 10 ms 20 ms 100 ms 20 ms 6 v 6 v 10 s por por internal logic start internal logic 1st dc-dc converter operation start 1st dc-dc converter 2nd dc-dc converter operation start 2nd dc-dc converter protection mask end protection mask ort ort serial data acceptable
TB62217AFG 2004-11-12 35 maximum ratings (ta = 25c) characteristics symbol rating unit remark motor output voltage v m 50 v i ost 1.3 a/phase stepper i osap 8 ? a dc motor s (500 ns) motor output current (note 1) (note 2) i osae 3 a dc motor s (100 ms) i co a 750 ma i dc b 400 ma dc-dc converter output current i dc c 400 ma current detection pin voltage v rs vm 4.5 v reset pin supply voltage v rst 5 v reset output current i rst ? 60 ma logic input voltage v in ? 0.4 to 6.0 v 1.25 w when ta exceeds 25c, this figure must be de-rated by 10.0mw /c. (note 3) power dissipation p d 4.2 w when ta exceeds 25c, this figure must be de-rated by 33.65mw /c. (note 4) operating temperature t opr ? 40 to 85 c storage temperature t stg ? 55 to 150 c junction temperature t j 150 c note 1: see other tables for pairing. note 2: peak maximum during dc motor drive (below 500 ns) note 3: stand-alone measurement (ta = 25 c) note 4: when the ic is mounted on a dedicated board (ta = 25 c) ta: ic ambient temperature topr: ic ambient temperature during operation t j : ic chip temperature during operation the maximum t j value is limited by the tsd (therma l shut-down circuit) temperature
TB62217AFG 2004-11-12 36 recommended operating conditions (ta = 0 to 85c) characteristics symbol test condition min typ. max unit excluding motor block 6 (note 1) 27 40 v vm supply voltage v m motor block 18 27 40 i ola stepper per phase (in single-ax is drive) at ta = 25 c ? 0.6 1.0 per h-bridge with peak of 500 ns at ta = 25 c ? 0.8 6.4 output current i osl dc per h-bridge with pulse of 100 ms at ta = 25 c ? 0.8 2.4 a i dci a (note 2) before the ort signal is output ? ? 100 ma dc-dc converter initial output current i dci b i dci c (note 2) before the ort signal is output ? ? 100 ma i dc a after the ort signal is output ? ? 600 ma dc-dc converter output current i dc b i dc c after the ort signal is output ? ? 300 ma logic input voltage v in ? gnd 3.3 5.0 v clock frequency f clk 1.0 ? 25 mhz motor chopping frequency range fchop ? 100 ? khz ? ? ? 800 ? ? vref reference voltage input range v ref vm = 40 v 0.8 2.0 3.0 v note 1: a voltage of 7 v or higher is recommended for typical use. a vm voltage range between 6 v (por voltage) and 7 v inclusive allows the dc-dc converter to exhibit much the same characteristics as when vm = 7 v (except that the vo ltage error becomes 10%). however, it is recommended to use the ic at 7 v or higher (partly to allow for a margin of stability), because both the rising por (power-on reset voltage) and falling por (shut-down voltage) are 6 v. note 2: when the power is turned on, soft start is put in effect by limiting the current to the dc-dc converter input block. the limited current results in the output current being limited. if an attempt is made to turn on the power with a load current flowing, it is likely that the dc-dc converter may fail to start or that the output voltage may abruptly increase when the soft-start current is switched.
TB62217AFG 2004-11-12 37 motor block electrical characteristics 1 (unless otherwise specified, ta = 25c and vm = 18v ~ 40 v) characteristics symbol test circuit test condition min typ. max unit high vih 2.0 ? ? logic input voltage low vil dc clk, strobe, data, enable, sleep, and phase logic input pins ? ? 0.8 logic input clamp voltage vik iik = ? 10 ma ? ? ? 0.4 v logic input hysteresis vin(his) dc clk, strobe, data, enable, and sleep input pins 0.1 0.2 0.3 v iin(h) ? ? 60 logic input current iin(l) dc vin = 3.3 v at each of the clk, strobe, data, enable, and sleep logic input pins ? ? 60 a im1 sleep mode sleep = l, all dc/dc = off (ic bias current) ? ? 2 operating current (vm pin) im2 dc sleep = h osc_d = 100 khz, motor = off dc/dc_a = off dc/dc_b = 1.5 v dc/dc_c = 3.3 v iout_chb + iout_chc = 10 ma ? ? 15 ma output standby current upper side ioh vrs = vm = 40 v, vout = 0 v, output off mode 0 ? 1 output leakage current lower side iol dc vrs = vm = vout = 40 v output off mode ?1 ? 1 a high (reference) vrs (hh) vref = 2.0 v, vref (gain) = 1/10, torque = (h.h) = 100% ? 100 ? middle high vrs (hl) vref = 2.0 v, vref (gain) = 1/10, torque = (l.h) = 85% 83 85 87 % middle low vrs (lh) dc vref = 2.0 v, vref (gain) = 1/10, torque = (h.l) = 70% 68 70 72 comparator reference voltage ratio low vrs (ll) vref = 2.0 v, vref (gain) = 1/10, torque = (l.l) = 50% 48 50 52 output current difference between channels in constant-current mode ? iout1 dc output current difference between adjacent channels at iout = 600 ma ? 5 ? 5 % constant-current output setting difference ? iout2 dc iout = 600 ma ? 5 ? 5 % rs pin current irs dc vrs = 40 v, vm = 40 v ? ? 10 a ron (d-s) 1 iout = 0.6 a, t j = 25 c, normal direction ? 0.6 0.72 ron (d-s) 1 iout = 0.6 a, t j = 25 c, reverse direction ? 0.6 0.72 ron (d-s) 2 iout = 0.6 a, t j = 105 c, normal direction ? 0.78 1.01 on-state resistance between motor output transistor drain and source ron (d-s) 2 dc iout = 0.6 a, t j = 105 c, reverse direction ? 0.78 1.01 ?
TB62217AFG 2004-11-12 38 motor block electrical characteristics 2 (unless otherwise specified, ta = 25c and vm = 18v ~ 40 v) characteristics symbol test circuit test condition min typ. max unit vref input voltage vref dc when motor output is active 0.8 ? 3.0 v vref input current iref dc when motor output is inactive and vref = 2.0 v ? ? 1.0 a vref (gain10) 1/9.6 1/10 1/10.4 vref attenuation ratio vref (gain20) dc when motor output is active and vref = 2 v 1/19.2 1/20 1/20.8 ? vmr (up) ? ? 14 15 motor power return voltage vmr (down) dc 13 14 ? v recommended capacitance for osc_m pin cosc_m ? external capacitance at fosc_m = 800 khz ? 220 ? pf operating current for motor over current protection circuit isd (note) dc fchop = 100 khz 3.0 5.0 6.0 a note: over current protection circuit if an abnormal current higher than the corresponding rating flows through a motor, the overcurrent protection circuit triggers the internal shut-down circuit to turn o ff the output block. in this case, the currently latched function data is cleared. the overcurrent protection circuit is kept tripped for t he motor block until (1) the power is turned on again or (2) the sleep returns to a high level. if isd comes in effect, the output becomes inactive (all off state) and is kept so until a normal condition is recovered. however, be sure to insert a fuse into the power supply for sake of fail-safe.
TB62217AFG 2004-11-12 39 electrical characteristics dc_3 (unless otherwise specified, ta = 25c, vm = 18v ~ 40 v, and motor iout = 1.0 a) characteristics symbol test circuit test condition min typ. max unit a = 90 ( 16) ? 100 ? a = 84 ( 15) ? 100 ? a = 79 ( 14) 93 98 ? a = 73 ( 13) 91 96 ? a = 68 ( 12) 87 92 97 a = 62 ( 11) 83 88 93 a = 56 ( 10) 78 83 88 a = 51 ( 9) 72 77 82 a = 45 ( 8) 66 71 76 a = 40 ( 7) 58 63 68 a = 34 ( 6) 51 56 61 a = 28 ( 5) 42 47 52 a = 23 ( 4) 33 38 43 a = 17 ( 3) 24 29 34 a = 11 ( 2) 15 20 25 a = 6 ( 1) 5 10 15 chopper current vector ? dc a = 0 ( 0) ? 0 ?
TB62217AFG 2004-11-12 40 electrical characteristics dc_4 (unless otherwise specified, ta = 25c and vm = 40 v) characteristics symbol test circuit test condition min typ. max unit internal logic supply voltage vcc dc (automatically created within the ic) external capacitance: under consideration 4.5 5.0 5.5 v tsd operating temperature t j tsd (note 1) dc ? 130 150 170 c ? 20 c (serial setting) 110 150 ? 30 c (serial setting) 100 140 pre tsd detection temperature pre tsd dc ? 30 c (serial setting) 90 130 c vtho (h) h 3.2 ? ? th_out output voltage vtho (l) l 0 ? 0.4 v lo (h) h 3.2 ? ? logic out lo (l) l when pull up to 3.3 v with an external resistance of 1 k ? 0 ? 0.4 v note: the maximum t j should not exceed 120 c. thermal shut-down (tsd) circuit tsd comes in effect if the ic juncti on reaches a rated temperature. it c auses the internal reset circuit to operate, thus turning off the ou tput block. (only one tsd ci rcuit is mounted on the ic.) the tsd operating temperature can be set anywhere in a range between 130 c (min) and 170 c (max). when tsd comes in effect, the currently latched func tion data is initialized and the output is stopped. once the supply voltage drops to or below the por voltage to shut down the ic, increasing the supply voltage above the por reset voltage initializes and restarts the ic.
TB62217AFG 2004-11-12 41 dc-dc converter block elect rical characteristics (t j = 0 to 120c and vm = 7 to 40 v) characteristics symbol test circuit test condition min typ. max unit output voltage error ? vout dc vm = 6.5 v~40 v t j = 0~120c 0.5 ma~600 ma (large) 0.5 ma~300 ma (small) dcdc output = 1.5 to 5 v ? 7.0 0 7.0 % vm = 40 v, upper side ?0.1 ? 0.1 dc-dc converter output-off leakage current iol_dc dc vm = 40 v, lower side ?0.1 ? 0.1 a ron (ds) a1 iout = 300 ma, t j = 25 c, reverse direction ? 0.7 0.84 on-state resistance between output transistor drain and source (large dcdc unit: ach) ron (ds) a2 dc iout = 300 ma, t j = 105 c, reverse direction ? 0.9 1.1 ? ron (ds) bc1 iout = 150 ma, t j = 25 c, reverse direction ? 1.4 1.7 on-state resistance between output transistor drain and source (small dcdc unit: b, cch) ron (ds) bc2 dc iout = 150 ma, t j = 105 c, reverse direction ? 1.8 2.2 ? ilim (l) dc (large) 0.8 1.2 1.6 current limiter value (steady state) ilim (s) dc (small) ? 0.5 0.6 0.85 a ilim (l) dc (large) 0.2 0.3 0.4 current limiter value (starting) ilim (s) dc (small) ? 0.2 0.3 0.4 a vsd (u) + 30 + 40 + 50 vsd (l) dc in reference to the set voltage. the current limiter is inactive. ? 40 ? 30 ? 20 % vsd (lu) + 30 + 40 + 50 abnormal-voltage protection circuit vsd (ll) in reference to the set voltage. the current limiter is active. ? 20 ? 15 ? 5 % osc_d capacitor value cosc_d ? external capacitor value 47 120 ? pf feedback voltage vfb dc ? ? 1.5 ? v dc/dc a, b, cch all off ? 0 0.8 dc/dc a, bch on 1.25 2.5 3.75 c_select voltage vc_sel dc dc/dc bch, cch on 4.5 5.0 ? v reset block electrical characteristics dc (t j = 0 to 120c and vm = 7 to 40 v) characteristics symbol test circuit test condition min typ. max unit v mr (all, up) rising side. all functions change from off to on. 5.2 ? 6.0 por output voltage for vm supply voltage detection v mr (all, down) dc falling side. all functions change from on to off. 5.2 ? 6.0 v ort signal output current i rst dc reset pin voltage = 0.4 v 2 ? ? ma vort (h) 3.2 ? ? ort output pin voltage vort (l) dc pulled up to 3.3 v with an external resistance of 1 k ? 0 ? 0.4 v
TB62217AFG 2004-11-12 42 motor block ac electri cal characteristics (ta = 25c, vm = 40 a, and motor impedance = 6.8 mh/5.7 ? ) characteristics symbol test circuit test condition min typ. max unit input clock frequency fclk ac vin = 3.3 v clk input pin 1.0 ? 25 mhz tw (clk) 40 ? ? twp (clk) 20 ? ? minimum clock pulse width twn (clk) ac vin = 3.3 v 20 ? ? ns tstrobe 40 ? ? tstrobe (h) 20 ? ? minimum strobe pulse width tstrobe (l) ac vin = 3.3 v 20 ? ? ns tsusin-clk 10 ? ? ns data setup time tsust-clk ac vin = 3.3 v 10 ? ? thsin-clk 10 ? ? data hold time thclk-st ac vin = 3.3 v 10 ? ? ns tr(s) 0.1 0.3 0.5 tf(s) 6.8 mh/5.7 ? load (small mode) 0.1 0.3 0.5 tr(l) 0.1 0.3 0.5 tf(l) 6.8 mh/5.7 ? load (large mode) 0.1 0.3 0.5 tplh (stb) ? 15 ? tphl (stb) step motor mode 6.8 mh/5.7 ? load between strobe ( ) and out ? 10 ? tplh (oscm) ? 1.2 ? tphl (oscm) step motor mode 6.8 mh/5.7 ? load between osc down edge and out 2.5 tplh (ena) 0.3 ? 0.9 tphl (ena) dc motor mode between enable edge and out 0.3 ? 0.9 tplh (phase) 0.3 ? 0.9 output switching time tphl (phase) ac dc motor mode between phase edge and out 0.3 ? 0.9 s noise rejection analog dead band time tblank (analog) ac iout = 0.6 a 200 300 400 ns motor chopper reference signal oscillation frequency f osc_m ac c_osc_m = 220 pf 600 800 1000 khz fchop (min) fchop (typ.) frequency range in which motor chopping is supported fchop (max) output active (iout = 0.6 a) with fixed steps 40 100 150 khz motor chopping setting frequency fchop (m) ac output active (iout = 0.6 a) m_osc clk = 800 khz ? 100 ? khz
TB62217AFG 2004-11-12 43 control signal timing chart 50% 50% 50% tphl(phase) tplh(phase) phase out a - out a + 50% 50% tplh(ena) tphl(ena) enable out a + 50% t !# phase out a c!# tw(clk) twn(clk) twp(clk) 50% 50% tsust-clk tstrobe(h) thclk-st tstrobe(l) tstrobe thclk-st tsusin-clk 50% 50% data15 data0 50% 90% 50% 10% tr tf tphl(stb) tplh(stb) tphl(oscm) tplh(oscm) clock strobe data 50 ? oscm out a - out a + fosc_m data1
TB62217AFG 2004-11-12 44 dc-dc converter ac elect rical characteristics (t j = 0 to 120c and vm = 40 v) characteristics symbol test circuit test condition min typ. max unit tr_d(l) ? 0.1 ? output transistor switching characteristic (large) tf_d(l) ac vm = 40 v, dcdc ach (large) ? 0.1 ? s tr_d(s) ? 0.1 ? output transistor switching characteristic (small) tf_d(s) ac vm = 40 v, dcdc b/cch (small) ? 0.1 ? output transistor feed-through prevention time toff ac vm = 40 v 100 300 ns dc-dc setting frequency fchop_d (osc_d) ac ? ? 100 200 khz protection circuit dead band (mask) time at startup tstrart _mask ac the dc-dc converter is turned on independently of others, using serial data. fosc_m = 800 khz and after the strobe signal has been accepted ? 100 ? ms initial startup delay time tstart1 ac at fosc_m = 800 khz and after vm becomes 6 v or higher but before the first dc-dc converter starts. ? 20 ? ms initial startup delay time 2 tstart2 ac at fosc_m = 800 khz and after the first dc-dc converter has started but before the second dc-dc converter starts. ? 20 ? ms startup soft mode period tsoft ac fosc_m = 800 khz ? 20 ? ms lvco detection dead band time tlvco ac at fosc_m = 800 khz and after vm becomes 6 v or lower but before the ort becomes low. ? 10 ? s por detection dead band time tpor ac at fosc_m = 800 khz and after vm becomes 6 v or lower but before the internal logic starts. ? 10 ? ms 90% 10% tr d(l) tr d(s) tf d(l) tf d(s) strobe dc/dc output mask signal tstart_mask active non - active active non - active oscd fchop_d h l vm odx dgnd pch gate nch gate pch g) nch g) c off active non - active active non - active
TB62217AFG 2004-11-12 45 other electrical characteristics ac (t j = 0 to 120c and vm = 7 to 40 v) characteristics symbol test circuit test condition min typ. max unit startup reset release time 1 (protection mask time) trst1 (init) ac from vm power-on por release fosc_m = 800 khz (114688 clock pulses) ? 140 ? ms startup reset release time 2 (with no dc-dc converter in use) trst2 (dcdc off) ac from vm power-on por release fosc_m = 800 khz (262144 clock pulses) ? 320 ? ms ort output low-pulse width when the motor isd is active trst(on) ac fosc_m = 800 khz (32768 clock pulses) 40 ? ? ms ort signal output delay time trst (delay) ac irst = 20 ma pulled up to cc with a resistance of 200 ? ccc = 0.1 f ? 50 ? ns internal initial setup timing tinit_time ac fosc_m = 800 khz after por release ? 10 ? ms sleep pulse width tsleep (on) ac fosc_m = 800 khz 10 ? ? s sleep release delay time tsleep (delay) ac fosc_m = 800 khz ? ? 10 s por active non - active active non - active vm por tpor *oufsobmmphjd t_start1 t_start2 t_soft t_soft 1 ? stdc/dc 2 ? nddc/dc ort trst1 / trst2 tinit_time active non - active non - active active h l 0wfsdvssfou efufdujpo non - active active non - active active ort trst on) trst delay) tlvco
TB62217AFG 2004-11-12 46 calculating the motor setting constant current the motor setting current value is determined by r rs and vref as follows: iout (max) = vref (gain) vref (v) 100% ) ( r ) : 50% 70, 85, 100, (torque torque rs ? = ??3?????? assume, for example: vref (gain) = 1/10: the attenuation ratio is typically 1/10 when vref = 1/10. vref = 2 (v) torque = 100 (%) producing iout = 1.0 a requires r rs = 0.20 ? (at least 0.2 w). the vref (gain) is fixed at 1/10 for stepping motors and selectable from 1/10 and 1/20 for dc motors. the error of constant current setting is 5 % when excluding vref and rs . calculating the osci llation frequency (chopping reference frequency) for th e motor and dc-dc converter blocks (1) calculating the osc reference frequency for the motor block (typical) fosc_m = 61820 c (pf) ^ ? 0.8043 (khz) hence, the osc frequency for the motor block is about 810 khz when cosc_m = 220 pf. the chopping frequency for stepping motors is about 1/8 the above frequency, that is, 810/8 (= 101) khz. in addition, only the fast decay mode is available for dc motor drive. (2) calculating the osc frequency for the dc-dc converter block (typical) f oscd = 5315.3 c (pf) ^ ? 0.8341 (khz) hence, the osc frequency for the dc-dc converter block is about 100 khz when cosc_d = 120 pf. input serial data
TB62217AFG 2004-11-12 47 power supply sequence (1) if c_select = low vm por all off full mode soft start mode 20 ms all clear dc/dc all off (c_sel = l) 10 ms 0 initialize por release 320 ms ort dc/dc control init data extended data dc/dc status vm voltage initial value active rewritten with serial data rewritten with serial data osc_m osc_d non-active h l re-writable all cleared re-writable all cleared active non-active active non-active
TB62217AFG 2004-11-12 48 (2) normal start (c_select = mid or high) vm por vm = 15.0 v all off full mode ort soft start mode 20ms all clear rewritten with serial data sleep dc/dc control motor driver control 10 ms 0 initialize dc/dc control start 10 ms por release note: por release initialize 10 ms initialize first dcdc start 10 ms dcdc soft start mode 20 ms initial value init data extended data dc/dc status re-writable re-writable vm voltage active off ( data cleared ) off (data cleared) operable (if vm = 15 v or higher) osc_m osc_d non-active ! controlled with serial data all cleared ! all cleared active non-active active non-active controlled by c select
TB62217AFG 2004-11-12 49 (3) if vm voltage drops at startup (c_select = mid or high) vm por dc/dc status all off soft start mode 20 ms 10 ms 0 below 10 s 10 ms all clear rewritten with serial data controlled by c_select ort dc/dc control controlled with serial data init data extended data full mode vm voltage initial value h initialize osc_m osc_d l re-writable all cleared re-writable all cleared active non-active active non-active all clear active non-active
TB62217AFG 2004-11-12 50 (4) vm voltage drop (normal) vm = 15.0 v all l all off por off (data cleared) 10 s full mode vm vm = 0 v re-writable active all off dc/dc status ort dc/dc control init data extended data vm voltage motor driver control operable (if vm = 15 v or higher) rewritten with serial data rewritten with serial data osc_m osc_d non-active h l all cleared re-writable all cleared active non-active active non-active active non-active
TB62217AFG 2004-11-12 51 (5) supply voltage drop (if the vm supply voltage does not cross the por level) ort = h motor driver control not operating (if vm = 15 v or lower) por vm = 0 v full mode vm = 15 v dc/dc status ort dc/dc control init data extended data vm voltage rewritten with serial data rewritten with serial data osc_m osc_d active non-active h l all cleared re-writable all cleared active non-active active non-active active non-active re-writable
TB62217AFG 2004-11-12 52 (6) supply voltage drop (if the vm supply voltage crosses the por level) por 10 s all off all = l rewritten with serial data rewritten with serial data rewritten with serial data not operating (if vm = 15 v or lower) soft start mode 20 ms 10 ms 10 ms active initialize dcdc start full mode full mode vm = 15 v vm = 0 v controlled by c_select shut down (all off) not operating (if vm = 15 v or lower) rewritten with serial data off (data = all l) all cleared re-writable initial value active motor driver control dc/dc status ort dc/dc control init data extended data vm voltage osc_m osc_d all = l non-active h l all cleared re-writable non-active active non-active active non-active
TB62217AFG 2004-11-12 53 mixed decay mode current waveform and setting in constant-current control, the current fluctuation widt h (current pulsating component) decay mode can be set to any of four points, 0 to 3, using 2-bit serial data. the abbreviation ?nf? stands for ?negative feedback?. it refers to a point where the output current has reached the set current value. the lower the mixed decay timing value, the lower is the current ripple component (current crest value), leading to a lower current decay ability. f chop 12.5% mixed decay cr pin internal clock waveform 37.5% mixed decay 75% mixed decay fast decay 100% nf charge mode nf: set current value reached slow mode mixed decay timming fast mode charge mode nf set current value mdt charge mode nf: set current value reached slow mode mixed decay timming fast mode charge mode set current value charge mode nf: set current value reached slow mode mixed decay timming fast mode charge mode nf charge mode nf: set current value reached fast mode 75% 50% 25% 0 decay mode 0 decay mode 1 decay mode 2 decay mode 3 set current value set current value mdt mdt
TB62217AFG 2004-11-12 54 relationships between the osc_m and output drive timing osc_m and charge delay a delay of up to 1.25 ns (when f chop = 100 khz and f cr = 800 khz) can occur between the osc waveform and internal osc_m clk, because the rising level of the osc waveform is used in converting the osc waveform to the internal m_clk. t chop osc-charge delay h l set current osc-fast delay fosc _m 50% 50% l h h l l charge 50% slow fast output voltage a output voltage a output current cr waveform internal m_clk cr-cr clk delay
TB62217AFG 2004-11-12 55 vsd threshold change timing during dc- dc converter block current limiter operation when the limiter enters an operating state, the vsd circuit starts operating if this state continues for 3 osc_d periods. osc_d osc_d_clk (internal signal) limiter operating state vsd threshold change (l: ? 15%) limiter operating state vsd threshold change (l: ? 15%) limiter operating state vsd threshold change (l: ? 15%) limiter operating state vsd threshold change (l: ? 15%) case 1 case 2 case 3 case 4 (3) (1) (1) (2) (1) (2) (3) (1) (2) (4) vsd detected shut-down normal operation continued normal operation continued normal operation continued
TB62217AFG 2004-11-12 56 output-stage transistor operation mode output-stage transistor operation functions clk u1 u2 l1 l2 charge on off off on slow off off on on fast off on on off note: the above table summarizes how each transistor behaves when the current flows in the indicated direction. the table below summarizes how each transistor behaves when the current flows in the opposite direction. clk u1 u2 l1 l2 charge off on on off slow off off on on fast on off off on u1 l1 u2 l2 pgnd off off note r s pin r rs v m on on load change mode u1 l1 u2 l2 off on note load pgnd slow mode on r s pin v m off r rs on u1 l1 u2 l2 note load pgnd fast mode r s pin v m off off on r rs
TB62217AFG 2004-11-12 57 pd-ta (package power dissipation) this item to be revised once package characteristics are fixed. thqfp64-p-1010-0.50 note: the board assumed in simulation is toshiba's ideal board (for reference only). temperature ( c) power dissipation p d (w) 0 0 5 50 100 150 175 1 2 3 4 25 75 125 rth (stand-alone) rth (4-layer board) (for reference only) transient thermal resistance of thqfp64 stand-alone and on a pc board (for reference only)
TB62217AFG 2004-11-12 58 operating time of the motor o ver current protection circuit (isd dead band time and isd operating time) reference diagram: timing chart showing over current flowing through a motor the over current protection circuit h as the dead band time to avoid detecting over current accidentally from current spikes in switching. the dead band time is in synchronization with the frequency of the osc for setting up the chopping frequency (osc_m). the time between the instant when over current star ts flowing through the outp ut stage and the instant when the output stops is as follows: when dead band time = 4 fosc_m period minimum: 4 fosc_m period maximum: 8 fosc_m period (+ synchronization time + 1 fosc_m time) however, the operating time stated ab ove applies when the over current fl ows ideally. the over current circuit may not work depending on the output control mode and timing. therefore, a protection fu se needs to be inserted in the vm power supply. (the required rating of the fuse varies depending on the conditions under which the ic is used. therefore, select a rating that will not cause the maximum power di ssipation of the ic to be exceeded and that will not pose any problem.) min max fosc_m oscillation (chopping reference waveform) output stop (reset state) dead band time isd blank time isd operating time time when over current starts flowing thr ough the output stage (over current state start) fosc (osc_m)
TB62217AFG 2004-11-12 59 application circuit example 0%# 7%*/ 7%*/ 7. '## $$ '# -(/% 0%" $ @ 4 & - & $ 5 1)"4&4" 1)"4&4# 1)"4&4% &/"#-&4" &/"#-&4$ &/"#-&4% 035 04$. 5i@065 -0(*$@065 73&'4$% 1)"4&4$ -(/% 5&45 73&'4"# 04$% 0%$ '#$ 0 6 5 4 % . ( / % 3 4 % 3 4 % 0 6 5 4 % . ( / % 0 6 5 4 $ 3 4 $ 3 4 $ 0 6 5 4 $ . ( / % . ( / % % ( / % 4 - & & 1 0 6 5 " . ( / % 3 4 " 3 4 " 0 6 5 " . ( / % 0 6 5 # 3 4 # 3 4 # 0 6 5 # . ( / % . ( / % % ( / % for c_sel:2.5v 200kohm q' v' v' q' m m 7. 7
3.3v 7 lpin lpin lpin pin pin pin pin v) v) ) v' v' v' m m &/"#-&4# /$ /$ / $ / $ / $ / $ /$ /$ ? lpin lpin 7 lpin lpin 7 opuijoh pin 7 3"3#3$ 3"3#3$ 0vuqvu 7pmubhf 3$ 3$ 3# 3# 3" 3" from asic from asic from asic from asic from asic from asic from asic from asic from asic sbd
TB62217AFG 2004-11-12 60 marking j j a a p p a a n n 2 2 1 1 7 7 a a f f 2 2 6 6 g g a a 1 1 1 1 l l o o t t t t r r a a c c e e a a b b i i l l i i t t y y c c o o r r r r e e s s p p o o n n d d e e n n c c e e l l o o t t c c o o d d e e g g m m a a n n u u f f a a c c t t u u r r e e y y e e a a r r 1 1 f f i i g g u u r r e e w w e e e e k k l l y y p p r r o o d d u u c c t t i i o o n n f f a a c c t t o o r r y y t t o o s s h h i i b b a a o o i i t t a a f f a a c c t t o o r r y y w w a a f f e e r r / / a a s s s s e e m m b b l l y y t t r r a a c c e e a a b b i i l l i i t t y y c c o o d d e e 1 1 p p i i n n t t o o s s h h i i b b a a c c o o u u n n t t r r y y o o f f m m a a n n u u f f a a c c t t u u r r e e w w e e e e k k l l y y c c o o d d e e p p r r o o d d u u c c t t n n a a m m e e t t b b 6 6 2 2 ~ ~ o o m m i i t t t t e e d d . . v v e e n n d d o o r r n n a a m m e e ( ( t t o o s s h h i i b b a a ) ) 1 1 p p i i n n m m a a r r k k
TB62217AFG 2004-11-12 61 package dimensions (thqfp64-p-1010-0.50) weight: 0.45 g (typ.) note: the heat sink provided on the bo ttom surface of the package is 5.5 mm 5.5 mm (tentative). heat sink

▲Up To Search▲

Price & Availability of TB62217AFG

	To Download TB62217AFG Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .